System-in-package (SIP) is an integration approach that is often utilized to achieve intelligent partitioning of the key components of an electronics system to achieve increased functionality using smaller form factors. One implementation of SIP technology applies three-dimensional integration, whereby two or more semiconductor die are stacked on top of each other so as to increase the amount of circuitry that may exist per unit area.
Die stacking involves a process whereby a base die, such as a field programmable gate array (FPGA), provides a platform for one or more stacked die, such as random access memory (RAM) or a microprocessor. Interconnections between the base die and the one or more stacked die may be implemented using a plurality of implementations, such as using micro-bumps or wire bonds.
The inter-die connections may be facilitated through the use of programmable heterogeneous integration (PHI), which is disclosed in U.S. patent application Ser. No. 11/973,062, filed on Oct. 4, 2007 by Rahman et al, assigned to the assignee of the present invention and which is incorporated herein by reference in its entirety. In general, a PHI tile consists of programmable multiplexers, through-die vias (TDVs), level translation circuits, test circuits, and dedicated power supply ports. A PHI tile is used to interconnect a base die having specific patterns of TDVs and associated input/output (I/O) pads with one or more stacked die having I/O pads that match the I/O pad placements of the base die. Signals existing within the stacked die may then be propagated to the base die using the associated TDVs, I/O pads, and level translation circuitry as may be required in a particular application.
Turning to FIG. 1A, a cross-section of stacked-die package 100 is exemplified, whereby one or more flip-chip packages may be assembled using micro-bump interconnection. In particular, the active side of stacked die 106 contains an array of pads upon which solder bumps 110 are attached. Base die 104 similarly contains a corresponding array of pads, which electrically combine with solder bumps 110 to form the interconnection between stacked die 106 and base die 104.
Base die 104 also contains an array of pads upon which solder bumps 108 are attached. Package substrate 102 similarly contains a corresponding array of pads, which electrically combine with solder bumps 108 to form the interconnection between base die 104 and package substrate 102. Package substrate 102 also provides the required interconnect structure so as to interconnect solder bumps 108 with ball grid array 122 of stacked-die package 100. Ball grid array 122 is then used to interconnect stacked-die package 100 to a circuit board (not shown) in order to facilitate signal exchange between stacked die 106, base die 104, package substrate 102 and the signal trace layers (not shown) of the circuit board.
Various test procedures exist, whereby the functionality of stacked-die package 100 may be verified. However, the functionality of TDVs 112 must also be verified, so as to test the continuity of connections formed between stacked die 106 and interconnect 120, logic 114, and power supply layers 116, 118 via TDVs 112 of base die 104. In particular, scan chains, or loop backs, may be instantiated using the programmable multiplexers of the PHI tiles that may be used to interconnect base die 104 with stacked die 106. In such an instance, a scan chain may be created, whereby a continuity signal is sequentially exchanged between each I/O connection of base die 104 and the corresponding I/O connection of stacked die 106 until the continuity of all I/O connections is verified.
Scan chain testing is an effective method to verify the interconnections between two or more stacked die, so long as a one-to-one correspondence exists between each input connection of the base die and the corresponding output connection of the stacked die under test and/or between each output connection of the base die and the corresponding input connection of the stacked die under test. Turning to FIG. 1B, an exemplary inter-die interface is illustrated, in which the number of input pads of stacked die 106, e.g., pads 188, 192, and 196, is equal to the number of output pads of base die 104, e.g., 176, 180, and 184, and the number of output pads of stacked die 106, e.g., 190, 194, and 198, is equal to the number of input pads of base die 104, e.g., 178, 182, and 186.
During scan chain testing of the inter-die interface of FIG. 1B, signal SELECT is asserted such that multiplexers 152-156 and 170-174 of their respective PHI tiles select their respective first input terminals as the active input terminal. As such, signal TEST IN is applied to the first input terminal of multiplexer 152 of base die 104 and propagates throughout the interconnect structure between base die 104 and stacked die 106 via TDV 158, output pad 176, input pad 188, multiplexer 170, output pad 190, input pad 178, and so on, until signal TEST IN emerges from TDV 168 as signal TEST OUT. In such an instance, the continuity of the entire interconnect structure between base die 104 and stacked die 106 is verified. If signal TEST OUT does not emerge from TDV 168, on the other hand, the continuity test of the interconnect structure between base die 104 and stacked die 106 is deemed a failure. In such an instance, the length of the scan chain may be reduced in order to isolate the failure.
Under normal operating conditions, signal SELECT is deasserted such that multiplexers 152-156 and 170-174 of their respective PHI tiles select their respective second input terminals as the active input terminal. In such an instance, the signals, e.g., NORMAL, are allowed to propagate through the interconnect structure between base die 104 and stacked die 106 as required to implement their respective functions during normal operating conditions.
Should a mismatch exist, however, between the number of input connections of the base die and the number of output connections of the base die and/or the number of output connections of the stacked die and the number of input connections of the stacked die, then a scan chain test fails to function as designed. In particular, certain of the interconnects between the base die and the stacked die are left unverified due to the interconnect mismatch.
Efforts continue, therefore, to provide greater flexibility of inter-die connections, so as to facilitate complete continuity testing between two or more stacked die having mismatched I/O connections.